1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including an inductor and a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device formed on an silicon-on-insulator (SOI) substrate which includes a buried oxide film and an SOI layer deposited on a silicon substrate (such semiconductor device will be hereinafter referred to as an “SOI device”) is characterized by a lower parasitic capacitance, a high-speed and reliable operation, and lower power consumption, and is used in a portable equipment or the like.
One example of an SOI device is an SOI device with a “full-trench isolation (FTI) structure”. In SOI device with the FTI structure, a trench reaching a buried oxide film is formed in a surface of an SOI layer and is filled with an insulator (which will hereinafter be also referred to as a “full-trench isolation film”), to electrically separate elements from each other. In the SOI device with the FTI structure, however, carriers (holes in an NMOS device) generated due to impact ionization are most likely to be accumulated in a channel region (where channel is to be formed). As such, the SOI device with the FTI structure has suffered from various problems associated with floating body effects. For example, a kink occurs, a breakdown voltage is reduced, or a delay time becomes frequency-dependent because of unstable potential of the channel region.
To overcome the foregoing problems, a “partial-trench isolation (PTI) structure” has been invented. The PTI structure is formed by forming a trench in a surface of an SOI layer while leaving a portion with a predetermined thickness of the SOI layer un-removed between a bottom of the trench and a buried oxide film, and filling an insulator (trench isolation film) into the trench.
The PTI structure allows carriers to move through a well region under the trench isolation film. Accordingly, accumulation of the carriers in a channel region can be prevented. Also, the potential of the channel region can be fixed because of existence of the well region, so that the above-cited various problems associated with floating body effects can be avoided.
In the meantime, in forming a high-frequency analog circuit or the like, an inductor, a capacitor, a resistor, and the like are employed as passive elements, in addition to a transistor as an active element.
For example, Japanese Patent Application Laid-Open No. 9-289324 (which will hereinafter be referred to as “JP 9-289324”) discloses forming a polysilicon resistor on a LOCOS oxide film (an oxide film formed by local oxide of silicon), at the fifth and sixth columns and FIG. 2(g).
When an SOI device with the PTI structure includes a spiral inductor, a full-trench isolation film is formed in an SOI layer in a region which is located under the inductor. Then, resistive elements are formed on the full-trench isolation film.
The spiral inductor has a cross section shaped like a rectangle having sides each with a length in a range between several tens of micrometers to several hundreds of micrometers. Thus, to form the full-trench isolation film under the spiral inductor means that the full-trench isolation film extends over a wide region corresponding to a footprint of the spiral inductor.
Then, to perform a chemical mechanical polishing (CMP) process for completing the full-trench isolation film in the above-described SOI device would cause the full-trench isolation film to be over-polished and removed in an amount larger than required. As a result, so-called dishing occurs. More specifically, a thickness of the full-trench isolation film decreases as a distance to a center thereof decreases. To form the resistive elements on the full-trench isolation film in which dishing is occurring causes undesired change in dimension or shape of some of the resistive elements which are located in the vicinity of an edge of the full-trench isolation film.
One possible solution to the foregoing undesired change is to avoid forming a resistive element in the vicinity of the edge of the full-trench isolation film. However, this solution requires increase in area of the full-trench isolation film in order to form the necessary number of resistive elements. As a result, a total area of the device is increased.
Also, if excessive dishing occurs in the CMP process, not only the isolation film and the SOI layer, but also an underlying buried oxide film, is probably polished. Further, a silicon substrate may possibly be polished.
A conventional solution for avoiding occurrence of dishing is to form plural dummy-element sites separately from one another in a region under the spiral inductor and its neighborhood, as disclosed by Japanese Patent Application Laid-Open No. 2002-110908 in the sixth column and FIGS. 3 and 4 (which will hereinafter be referred to as “JP 2002-110908”), for example.
As described above, the problem of occurrence of dishing must be faced with in forming a trench isolation film having a large area. In this regard, the structure disclosed by JP 2002-110908 which avoids occurrence of dishing by forming plural dummy-element sites separately from one another in a region where the trench isolation film is supposed to be formed, would not permit provision of the resistive elements in the corresponding region. Hence, the structure disclosed by JP2002-110908 is unsuitable for a high-frequency analog circuit or the like.